The present invention relates in general to semiconductor devices and, more particularly, to power transistors.
In Lateral Double Diffused Metal Oxide Semiconductor (LDMOS) power transistors, drain and source semiconductor regions are typically interdigitated regions formed on the same die surface to extend across the LDMOS transistor die, with bonding pads arranged around the die periphery. Final metal conductor regions extend across the drain and source semiconductor regions to connect the semiconductor regions to respective bonding pads. Since some of the current must follow the length of the drain or source region to the bonding pad, such power transistors have undesirably high on-resistance (RdsON).
One solution to reduce the resistance (RdsON) of power transistors is to have alternating metal strips formed over and coupled to source and drain semiconductor regions. A plurality of bumps is then formed on the metal strips for external connection to the source and drain regions of the power device. Since the distance between the bumps determines the distance of which current must travel from nearby source and drain regions, and minimum bump size determines the minimum metal strip width (thus spacing), and the distances current must travel is not minimized due to the constraint of bump size on current travel distance. For example, the average distance the current would travel is approximately one-half the distance between the centers of the bumps. Therefore, as resistance is proportional to the length or distance the current travels divided by the width of the metal strip, the RdsON of such as device is not optimized. Furthermore, if the device size is increased, the metal strip resistance increases as the metal strips traverse a greater device width.
Another solution utilizes a three metal layer solution wherein a plurality of source and drain regions are coupled together to form the source and drain of multiple LDMOS transistors. Each diffusion region has a first metal layer strip formed over and in contact with it, and a second metal layer strip formed over a plurality of the first metal layer strips to form source and drain busses. Then a third very thick metal layer is formed over the second layer metal busses to provide reduced metal line resistance and an external electrical contact for the power device. Since the lengths of the first and second metal layer strips must both be made greater as the size of the LDMOS power transistor increases, the resistance will also increase for reasons similar to those above. Furthermore, the third layer of metal requires additional complex and costly processing over the prior mentioned two metal strip solution. Moreover, as device size increase the metal interconnect layer resistance increases proportionally, as the busses or strips must traverse the entire width of the device.
Hence, there is a need for a power transistor that operates at a high current with a low on-resistance that is relatively independent of transistor size, that has a high power dissipation, and that can be made with a simple sequence of processing steps to maintain a low manufacturing cost.